The present invention relates to microelectronic elements such as semiconductor chips and structures incorporating the same.
Conventional semiconductor chips are fabricated by forming active semiconductor elements such as transistors and circuits incorporating the same on a crystalline wafer as, for example, a silicon wafer. The active devices are formed by processes such as epitaxial growth, doping, and the like, so as to form the active devices in a very thin layer, typically a few microns thick or less, on a front surface of the wafer. Additional elements such as conductors and resistors also may be formed on the wafer within the active layer, or in other layers close to the active layer. The active layer may include numerous sub-layers of elements. The wafer is further provided with electrically conductive contacts electrically connected to the components in the active layer. The wafer typically is provided with an inert layer commonly referred to as a “passivation” layer overlying the active layer and covering the front surface of the wafer, except at the contacts. Such a wafer is then cut into individual semiconductor chips, each of which incorporates a portion of the wafer including appropriate circuits and electrical contacts connected thereto. Thus, each chip has a front surface corresponding to the front surface of the wafer and an oppositely facing rear surface corresponding to the original rear surface of the wafer. The active elements and other functional components are disposed in the thin active layer near the front surface of the chip, and the contacts are exposed at the front surface of the chip. Most of the thickness of the chip is occupied by the inert material of the original wafer.
Semiconductor chips typically are mounted on a circuit panel, with the front or rear surface of the chip facing toward the circuit panel, and extending generally parallel to the face of the circuit panel. The chip may be mounted as such to a circuit panel. Most often, however, the chip is provided in or on a structure referred to as a chip package. The chip package may physically protect the chip and may provide conductive features which form interconnections between the contacts of the chip and the conductive elements of the circuit board.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, low-impedance interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.
Considerable effort has been devoted to reducing the dimensions of chips and packaged chips in the horizontal dimensions parallel to the front and rear surfaces of the chip, also referred to as the “X” and “Y” directions, so as to minimize the area of the circuit board occupied by the chip or packaged chip. So-called “stacked” chip arrangements have also been employed. In a stacked chip arrangements, plural chips are disposed one above the other, so that the stack extends in a vertical direction. Such a stack may be formed by providing multiple chips in a single package, which is then mounted to a circuit board, or by providing multiple chip packages arranged so that the chip packages can be stacked one atop the other. This arrangement minimizes the total area occupied by the various chips in the horizontal directions, but adds to the height or vertical dimension of the assembly, also referred to as the “Z” direction. A stacked arrangement should provide a simple and effective way of making the vertical connections between the various chips. The components which form the vertical interconnections ideally should not greatly increase the volume of the assembly.
As a general rule, any assemblage of multiple chips occupies a volume no less than the sum of the volumes of the individual unpackaged chips and often considerably more. It has long been recognized that the volume of an individual unpackaged chip, and consequently the volume of any assembly incorporating that chip, can be reduced by reducing the thickness of the chip. As mentioned above, much of the thickness of an individual chip is occupied by the inert material of the original wafer. Thus, it is common practice in the art to “thin” chips by removing some of the inert material of the wafer from the rear surfaces of the chips, either before or after the wafer is cut into individual chips. In current practice, some chips are thinned to about 100-200 microns. However, the thinning process cannot be continued without limit. Even though the electrically active components of the chip are contained within a thin layer at the front surface, the chip still must have sufficient thickness to provide physical stability during handling and processing. Moreover, simply thinning a chip does nothing to reduce the volume occupied by the interconnections between the chip and package or between the chip and other chips in a stacked arrangement.
Structures referred to herein as “composite chips” include a body with oppositely facing front and rear surfaces similar to a body of a conventional semiconductor chip and include a separately formed semiconductor layer bonded to the front surface of the body. The semiconductor layer may be a layer which is quite thin as, for example, on the order of 10 microns or less in thickness. Such a composite chip may be made, for example, by forming an active layer on a front surface of a first semiconductor wafer and bonding the front surface of that wafer to a second semiconductor wafer, also referred to as a “carrier wafer.” The first semiconductor wafer is thinned so as to leave only a very thin semiconductor layer including the active layer in place on the front surface of the carrier or second wafer, thereby forming a composite wafer. The composite wafer is then cut into individual composite chips. Structures of this nature are used, for example, in so-called “rear-surface illuminated” image sensors. In such a structure, the active components in the semiconductor layer include photosensitive components. The photosensitive components are exposed to light impinging on the surface of the semiconductor layer facing away from the carrier or body. Composite chips can be used, for example, in conjunction with ordinary semiconductor chips and can be mounted and packaged in ways generally similar to the mounting and packaging of ordinary chips.
Despite all of the effort devoted in the art to mounting and packaging of chips, still further improvement would be desirable.